(1) Field of the Invention
The present invention relates to the manufacture of semiconductor devices, and in particular, to split-gate flash memory cells and to a method of forming high density flash memory arrays using the same.
(2) Description of the Related Art
Various techniques of forming memory cells have been used in the semiconductor manufacturing industry to increase the density of flash memory arrays. One such technique is to share the source and drain regions interchangeably between adjacent cells on the same word line of a split-gate flash memory. For example, in the dual split-gate (DSG) shown in FIG. 1a, two floating gates of the cells (A) and (B) share the same source/drain(S/D). More specifically, and as seen more clearly in the cross-sectional view (1b) of the same substrate (10), the memory cell is a triple polysilicon split-gate structure in which the floating gate (30) above gate-oxide (20) is polysilicon level 1, control gate (50), separated from the floating gate by inter-gate oxide (40), is polysilicon level 2, and the word select gate (80), separated from the control gate by nitride layer (60) is: polysilicon level 3. It will be noted that third polysilicon (80) is isolated from both the floating gate and control gate by oxide spacer (70) as shown in the same Figure. Source/drain diffusions (13) are placed every two floating gates apart, thus improving density over the conventional cell, which has separated source and drain regions. Although two floating gates share the same word gate, source and drain regions, read and/or program to a single floating gate is possible because control gates are separated. Above each of the floating gates lies a control gate which controls the voltage of the individual floating gate by capacitance coupling. The control lines run parallel to the source/drain. Some of the disadvantages of the DSG cell are high program voltages of about 12V and also high voltages during read. A high control gate voltage of 12V is required during read operation when one of the floating gates is being accessed in order to mask out the effects from the other floating gate. Adjacent cells which may share the same diffusion or control gate voltages will be effectively disabled from the operation by suppressing the other floating gates with a very low xcx9c0 control gate voltage. The same kind of over-ride and suppress techniques are used during program in order to target a single floating gate cell. In this way, program and read operations can be performed on the high density, self-aligned dual-bit split-gate flash/EEPROM cell.
As described more in detail by Y. Ma, et al., in U.S. Pat. No. 5,278,439 the DSG shown in FIGS. 1a and 1b contains two bits, A and B, one in each cell. This can be better understood by considering FIGS. 1d and 1e with the key shown in FIG. 1c. (See also, Y. Ma paper on xe2x80x9cA Dual-bit split-Gate EEPROM (DSG) Cell in Contactless Array for single-Vcc Height Density Flash Memoriesxe2x80x9d). The cell has two floating gates, one control-gate (CG), one transfer-gate (TG), one common selected gate (SG), and the two bits share one pair of drain (D) and source (S). As shown in FIG. 1b, the CG and TG are structurally identical. The SG channel is formed by a split-gate located between CG and TG. The dual-bit cell is accessed by five terminals, as shown in FIGS. 1d and 1e. The conventions of the five active terminals are referred to as the left (90) or right (95) selected bit in the cell, as indicated in the same Figures. It will be apparent to those skilled in the art that in comparison with a conventional single-bit cell, the DSG""s cell size savings comes directly from the shared and self-aligned SG. Of the three directly connected channels (CG, SG, and TG) between the source and drain, two work as a transfer channel (17), one as control-channel (15) for the selected channel, as shown in FIG. 1b. During an address switch between the left and right bits in the cell, the CG and TG terminals exchange their functions, so do the terminals of drain and source. Within a cell, the two bits are reciprocally equal.
The various program (write), erase and read operations for a DSG are illustrated in FIGS. 2a-2c and 3a-3c. FIGS. 2a-2c schematically represent the cross-sectional views of a DSG while FIGS. 3a-3c represent a top view of the same DSG where Figure numbers with the suffixes (a), (b) and (c) refer to the write, erase and read operations, respectively. The key shown in FIG. 1c also apply to FIGS. 2a-2c and 3a-3c so that the five terminals shown in FIGS. 2a-2c would be impressed with voltage (V) appropriate to the particular gate corresponding to each one of the operations.
Thus, keeping the same reference numerals in FIGS. 1a-1e referring to similar parts throughout the several views in FIGS. 2a-2c and 3a-3c, FIGS. 2a and 3a show the program or write operation for the same DSG as before. The write operation is performed bit by bit and the programmed bit is selected by a selected gate or word line (80) and bit line (13). In the write operation, source-side-injection mechanism is used where the selected gate (SG) is only weakly turned on so as to just turn on channel of unselected cell (30u) while a higher voltage is used on control gate (CG) to provide higher vertical electric field to complete the write operation. In other words, hot-electrons (12W) are created at the transitional channel region (17) between SG and CG, and injected to the source side of the floating gate (30s) while TG and CG are strongly turned on. The various voltage levels are shown for the program operation in both FIGS. 2a and 3a. 
In the erase operation shown in FIGS. 2b and 3b, negative-gate Fowler-Nordheim tunneling is used. Thus, during erase, with negative voltage of xe2x88x9210V on CG, an applied drain voltage of 7V pulls the stored electrons out of floating gate (30s) via drain-side tunneling (12E), while the SG is grounded and the conduction channel cut off. As seen in FIG. 3b, erased bits (30s) are selected only by CG and a whole page of bits in the array are erased.
The read operation is accomplished by selecting the read bit by word line (80) and bit line (13) as in the write operation except that the TG and SG are fully turned on and the stored information is sensed by detecting whether the is channel current (12R) under the grounded CG.
In prior art there are other schemes for forming triple polysilicon flash EEPROM arrays with dual-bit capabilities. In U.S. Pat. Nos. 6,028,336 and 5,712,179 by Yuan, a triple polysilicon flash EEPROM array having a separate erase gate for each row of floating gates, and methods of manufacturing such an array are disclosed. As part of a flash EEPROM array on a semiconductor substrate, erase gates are formed in individual trenches between rows of floating gates. The erase gate is positioned along one sidewall of the trench in a manner to be capacitively coupled with the floating gates of one of the rows adjacent the trench but spaced apart from the floating gates of the other row adjacent the trench. In this way, a separate erase gate is provided for each row of floating gates without increasing the size of the array. The erasure of each row is then individually controlled. Two self-aligned methods of forming such an array are disclosed. One method involves forming a thick insulating layer along one sidewall of the trench and then filling a remaining space adjacent an opposite trench sidewall with polysilicon material forming an erase gate for the row of floating gates adjacent the other sidewall. A second method involves anisotropically etching a layer of polysilicon that is formed over the array in a manner to conform to the trench sidewalls, thereby separating the polysilicon layer into individual erase gates carried by the trench sidewalls.
In U.S. Pat. No. 6,13,098, a process for making and programming and operating a dual-bit multi-level ballistic flash memory is disclosed by S. Ogura. Here, two side wall floating gates are paired with a single word line select gate, and word lines are arranged to be perpendicular both the bit lines and control gate lines. Two adjacent memory cells on the same word line do not require an isolation region. Adjacent memory cells on the same word line share bitline diffusion as well as a third poly control gate. Control gates allow program and read access to the individual floating gate. In one embodiment, the dual multi-level structure is applied to the ballistic step split gate side wall transistor. In a second embodiment, the dual multi-level structure is applied to the ballistic planar split gate side wall transistor. Both types of ballistic transistors provide fast, low voltage programming. The control gates are used to override or suppress the various threshold voltages on associated floating gates, in order to program to and read from individual floating gates.
In still another dual floating gate EEPROM cell array, with steering gates that are shared by adjacent cells, E. Harari, et al., show in U.S. Pat. No. 6,151,248 how dual gate cells can increase the density of data stored. An EEPROM system has an array of memory cells that individually include two floating gates, bit line source and drain diffusions extending along columns, steering gates also extending along columns and select gates forming word lines along rows of floating gates. The dual gate cell increases the density of data that can be stored. Rather than providing a separate steering gate for each column of floating gates, an individual steering gate is shared by two adjacent columns of floating gates that have a diffusion between them. The steering gate is thus shared by two floating gates of different but adjacent memory cells. In one array embodiment, the floating gates are formed on the surface of the substrate. In arrays that erase the floating gates to the select gates, rather than to the substrate, the wider steering gates uncouple the diffusions they cover from the select gates. This use of a single steering gate for two floating gates also allows the floating gates, in another embodiment, to be formed on side walls of trenches in the substrate with the common steering gate between them, to further increase the density of data that can be stored. Multiple bits of data are also stored on each floating gate.
Low voltage erase of a flash EEPROM system having a common erase electrode for two individual erasable sectors are shown in U.S. Pat. No. 5,677,872 by G. Samachisa, et al. Here also a flash EEPROM is organized on an integrated circuit with individual erase gates being shared by two adjacent blocks, or sectors, of memory cells. This is to reduce the number of erase gates and the complexity of the driving erase circuitry.
Also, according to Guterman, et al., U.S. Pat. No. 6,222,762 teaches maximized multi-state compaction and more tolerance in memory state behavior through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. On the other hand, R. A. Cernea disclose in U.S. Pat. No. 6,091,633 a memory array architecture utilizing global bit lines shared by multiple cells. Multiple columns of memory cells are positioned between the global bit lines. Bit selection lines oriented in the column direction are connected to the gates of select transistors within the memory cells. Word line individually extend over one or two rows of floating gates. This arrangement provides a very small array that allows for future scaling.
As useful as dual-bit split-gates (DSG) and multi-state memory cells are, further improvements can be achieved by multi-sharing of source/drain regions in the manner disclosed below in the embodiments of the present invention.
It is therefore an object of the present invention to provide a multi-bit split-gate (MSG) flash cell with multi-shared source/drain.
It is another object of the present invention to provide a method of forming a multi-bit split-gate (MSG) flash cell with multi-shared source/drain.
It is still another object of the present invention to provide a method of programming a multi-bit split-gate (MSG) flash cell with multi-shared source/drain.
These objects are accomplished by a semiconductor substrate having a surface region of first conductivity type; a first drain region and a second drain region formed in said surface region; a plurality of (N+1) stacked gates separated apart by N select gates (SGs) between said first drain region and said second drain region, where N is any integer; a first bit line contacting said first drain region; a second bit line contacting said second drain region; and a word line contacting said select gate.
The objects of the instant invention are further accomplished by providing a semiconductor substrate having active and passive regions defined; forming a first dielectric layer over said substrate; forming a first polysilicon layer over said first dielectric layer; forming a plurality of floating gates comprising said first polysilicon layer, wherein said plurality of floating gates are spaced apart by a plurality of openings over said first dielectric layer; forming a second dielectric layer over said plurality of floating gates, including said plurality of openings; forming a second polysilicon layer over said second dielectric layer; forming a plurality of control gates comprising said second polysilicon layer over said second dielectric layer over said plurality of floating gates; forming a third dielectric layer over said plurality of control gates; forming a fourth dielectric layer over the inside walls of said plurality of openings; forming a third polysilicon layer over first of said plurality of openings to form a first bit line over said substrate, and over last of said plurality of openings to form a second bit line over said substrate; forming a fifth dielectric layer over said first bit line and over said second bit line; and forming a fourth polysilicon layer over said fifth dielectric layer, including over said plurality of openings, to form a word line contacting select gates on said semiconductor substrate.
Further objects for programming are accomplished by providing a multi-bit flash cell having a pair of source/drain (S/D) bit lines and Nxe2x80x2=(1+N) stacked gates comprising floating gates (FGs) and control gates (CGs) spaced apart with N select gates (SGs) between said bit lines, where N equals any integer; exchanging the address of control gates with those of transfer gates (TGs); performing program (write) operation bit by bit, wherein programmed bit is selected by word line, bit line and control gate; performing erase operation, wherein the erased bits are selected by word line, only; and performing read operation.